Lead-on-chip encapsulated modules such as those described in U.S. Pat. No. 4,862,245, issued Aug. 29, 1989 to Richard P. Pashby, et al. and assigned to the International Business Machines Corporation are well known in the art. These modules are comprised of a semiconductor chip having a plurality of bonding pads on one major surface, a dielectric layer joined to said surface and adjacent the bonding pads, and a plurality of lead frame conductors extending across the dielectric layer and ending immediately adjacent to the bonding pads. A gold wire is bonded to most of the bonding pads on the chip and extends from each respective pad to the bus bar or to each respective lead frame conductor. After bonding, the module is formed by the package encapsulation of the chips and leads in a hard plastic material.
An improved lead-on-chip device is shown in U.S. Pat. No. 5,151,559, dated Sep. 29, 1992 and issued to H. Ward Conru, et al. and assigned to the International Business Machines Corporation. In this improved device, a second dielectric, comprised of a thermal setting plastic, is forced down over the wires after the wires are bonded to the chip pads and the lead frame conductors and before encapsulation of the package. Forces are applied to the second dielectric layer to cause the wires underneath to be crushed down and held against the respective pads and leads to which they are connected. This improves the contact between the wire and the leads and minimizes defects or failures in wire bonding junctions. This improved device is particularly advantageous when used in a stacked semiconductor arrangement.
A problem of wire bond reliability occurs when lead-on-chip semiconductors are repeatedly exposed to a wide range of temperature variations. Such temperature cycling leads to expansion of the encapsulated materials. The resulting internal stress causes breaking of the wires or ruptures in the junctions between the wires and the lead frame or terminal pads.